| http://www.w3.org/ns/prov#value | - The semiconductor memory device of claim 12, wherein, if the first and N+1-th memory blocks are activated in the first memory bank, the K-th memory block is activated in the second memory bank, the 2K-th memory block is activated in the third memory bank, and the 3K-th memory block is activated in the fourth memory bank where K is an integer equal to or greater than 5.
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