| http://www.w3.org/ns/prov#value | - The calculator of claim 2 wherein said means for supplying said clock pulses to said shift register is arranged to supply rst and second out-of-phase trains of pulses, the pulses in each train being of constant width irrespective of the frequency of said clock pulses, and wherein each stage of said shift register contains first and second of said series circuits, each circuit including first and s
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