| http://www.w3.org/ns/prov#value | - Therefore, in order to minimize the regions where the disclination 400 occurs, as shown in FIG. 12, in the second embodiment of the present invention, grooves 10??? are formed in the shadowed regions of a plurality of pixel groups on the TFT array substrate shown in FIG. 13 so that wiring such as the data lines 6 a and the like, and TFTs 30 are partially buried in the grooves to planarize the subs
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