| http://www.w3.org/ns/prov#value | - Custom circuitry for reducing an L-bit data unit into an N-bit data unit selectable to include any combination of bits from the L-bit data unit, where L is an integer greater than two, N is an integer greater than one and L is greater than N, comprising:N successive multiplexors, each multiplexor receiving as inputs bits from M bit positions within the L-bit data unit including all but the first b
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