About: http://webisa.webdatacommons.org/366578806

Property	Value
http://www.w3.org/1999/02/22-rdf-syntax-ns#type	http://www.w3.org/ns/prov#Entity
http://www.w3.org/ns/prov#value	FIG. 19 is a timing chart showing an early write cycle of a regular DRAM. The early write cycle is characterized in that the trailing edge of the WE signal comes earlier than the trailing edge of the CAS signal.
http://www.w3.org/ns/prov#wasQuotedFrom	google.com