| http://www.w3.org/ns/prov#value | - Referring to FIG. 3, a memory cell block 100 includes memory cells (i.e., MLCs or SLCs) Me11 to MeJK and Mo11 to MoJK (J, K is an integer), drain select transistors DST and source select transistors SST. The MLCs Me11 to MeJK and Mo11 to MoJK have gates connected to word lines WL1 to WLJ, respectively.
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