About: http://webisa.webdatacommons.org/87970247

Property	Value
http://www.w3.org/1999/02/22-rdf-syntax-ns#type	http://www.w3.org/ns/prov#Entity
http://www.w3.org/ns/prov#value	FIG. 53 is a timing chart representing a state where the logic integrated DRAM 130 b operates in a full page mode of the register-DRAM transfer mode.
http://www.w3.org/ns/prov#wasQuotedFrom	google.com