| http://www.w3.org/ns/prov#value | - FIG. 12 is a timing chart for describing an operation of CMOS circuit 1200 of FIG. 11, wherein (a) shows inputs of precharge signal PRE and equalize control signals WEQ1 and WEQ2 in a standby state and an active state, (b) shows change in potential of N well line 2000 and P well line 2001 of circuit 1210, and (c) shows change in potential of N well line 2002 and P well line 2003 of circuit 1211.
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