| http://www.w3.org/ns/prov#value | - FIG. 53 is a timing chart showing the waveforms of a driving pulse TG supplied to the transfer transistor QTG (113), a driving pulse ??RSG supplied to a gate 114C of the reset transistor QRSG (114), and a driving pulse ??RSD supplied to a reset drain 114B of the reset transistor QRSG (114), together with the waveform of the electric signal Vout occurring at the source (node N1) of the JFET 112.
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