| http://www.w3.org/ns/prov#value | - FIGS. 8A and 8B show an example of a device structure in a case of connecting in parallel a plurality of the unit transistors Qu in the prior art shown in FIGS. 2A and 2B. FIG. 8A is a plan view in a case of connecting in parallel a plurality of the unit transistors Qu and FIG. 8B is a cross sectional view taken alone line X1-X1 in FIG. 8A in a case where the unit transistor Qu is an npn type.
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