About: http://webisa.webdatacommons.org/395460849

Property	Value
http://www.w3.org/1999/02/22-rdf-syntax-ns#type	http://www.w3.org/ns/prov#Entity
http://www.w3.org/ns/prov#value	This means that the leading edge of a pulse at its clock input (CK) causes the flip-flop to sample the one or zero condition, i.e. high voltage or low voltage condition at the D input thereto.
http://www.w3.org/ns/prov#wasQuotedFrom	patents.com