{ "items" : [
    { "id" : "http://webisa.webdatacommons.org/202877747"
      "properties" : {
        "http://www.w3.org/1999/02/22-rdf-syntax-ns#type" : [ "http://www.w3.org/ns/prov#Entity" ] ,
        "http://www.w3.org/ns/prov#value" : [ "For non-automatic cycle steal operations, data and other information can be transferred between the host processor and a microprocessor 33 via channel data bus 23, cycle steal data register (CSDR) 30 and a microprocessor data bus comprising Data Bus In (DBI) bus 34 and Data Bus Out (DBO) bus 35." ] ,
        "http://www.w3.org/ns/prov#wasQuotedFrom" : [ "google.com" ] } },

    { "id" : "http://webisa.webdatacommons.org/prov/208869219"
      "properties" : {
        "http://www.w3.org/ns/prov#wasDerivedFrom" : [ "http://webisa.webdatacommons.org/202877747"] } } }
