<http://webisa.webdatacommons.org/prov/30343174>	<http://www.w3.org/ns/prov#wasDerivedFrom>	<http://webisa.webdatacommons.org/87611070> .
<http://webisa.webdatacommons.org/87611070>	<http://www.w3.org/ns/prov#wasQuotedFrom>	<patents.com> .
<http://webisa.webdatacommons.org/prov/29617323>	<http://www.w3.org/ns/prov#wasDerivedFrom>	<http://webisa.webdatacommons.org/87611070> .
<http://webisa.webdatacommons.org/87611070>	<http://www.w3.org/1999/02/22-rdf-syntax-ns#type>	<http://www.w3.org/ns/prov#Entity> .
<http://webisa.webdatacommons.org/87611070>	<http://www.w3.org/ns/prov#value>	"FIGS. 8a and 8b are a circuit diagram showing an arrangement of a quaternary subtracter according to a third embodiment of the present invention." .