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  • A satellite clock system as defined in claim 8, wherein said means for determining an amount of phase error determines said phase error over an interval [t0, tn ] by sampling said phase error at sampling intervals of T0, where tn =t0 +T,T=nT0, and n is an integer, said predicted clock drift is determined for a succeeding interval [tn, tn +m], where m is an integer, and said error correction value
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