FIG. 1B is a circuit diagram illustrating the whole construction of a solid state image sensor comprising SITs shown in FIG. 1A. To drains (substrate) of SITs 1-11 to 1-mn forming pixels arranged in a matrix are commonly applied a video voltage VD, and to gate electrodes of SITs 1-11 to 1-1n; . . . ; 1-m1 to 1-mm arranged in the X direction, i.e. in row are connected row lines 11-1 to 11-m, respec