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  • The resulting data and address words, within which each block address consists of three 7-bit words, are supplied to latch circuits 6, 7 and 8 each of which is able to store one 7-bit word, to one input of a comparator 9, to a CRC circuit 10, and to an n block delay circuit 11 which delays the signals by n block periods, where n is an integer.
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