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  • Referring to FIG. 1, this PLLcircuit 1 includes a logic circuit 2 for selecting N kinds of oscillation circuits (where N is a positive integer) incorporated in the PLL circuit 1 by control data transmitted from a DC level decision circuit 8, an oscillation circuit 3 having N kindsof oscillation characteristics, a frequency-dividing circuit 4 for frequency-dividing a clock output from the oscillati
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