FIG. 5, FIG. 6, FIG. 7, FIG. 8, FIG. 9 and FIG. 10 are a series of schematic cross-sectional diagrams illustrating the results of forming upon a semiconductor substrate employed within an integrated circuit microelectronics fabrication a dual damascene conductor interconnection layer within an inter-metal dielectric (IMD) layer formed employing a low dielectric constant dielectric material, with a