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  • 3a is a functional block diagram of a master clock synchronization unit. [0046]FIG. 3b is a functional block diagram of a slave clock synchronization unit. [0047]FIG. 4 is a time division multiple access frame definition in accordance with the present invention. [0048]FIG. 5 is a functional block diagram of the Medium Access Control hardware interface of the present invention. [0049]FIG. 6 is a f
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