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  • As can be seen in FIG. 3B, a majority of the charge traps should be placed in close proximity to the channel, i.e. within 0.5 nm to 1.5 nm of the gate-dielectric/semiconductor interface, or tight at the interface itself This can be achieved using a low-energy implant of Boron at approximate dose of 2 to 3*1014 atoms/cm2.
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