| http://www.w3.org/ns/prov#value | - Eventually, at t3, the level of TG_OUT is down to Vss, the level shifter is disabled, and the supply level TG_IN is taken back down to Vdd. (Circuitry similar to that of FIG. 1 is discussed in U.S. Pat. No. 6,696,880, which also provides further discussion relevant to its operation and details on variations that can incorporated into the circuits of both FIG. 1 and FIG. 4, including techniques for
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