| http://www.w3.org/ns/prov#value | - Looking now to the detail of data cache 12 b shown in FIG. 2, it includes a cache controller 28 which receives a memory address, which in this case is a portion of a 32-bit data address DA[31:0], where the portion received includes bits ???[11:4]??? indicating that cache controller 28 receives bits ???4??? through ???11??? of the 32-bit address, and further receives bits DA[1:0], where similarly t
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