| http://www.w3.org/ns/prov#value | - This signal is a pulse signal having a pulse width substantially equal to the period of the signal CK-- OUT. This is because, at the next pulse of the clock signal CK-- OUT following a zero-valued signal XY, the value held by the register 628 and, thus the signal XY, becomes non-zero, causing the signal provided by the NOR gate 690 to become logic-low.
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