| http://www.w3.org/ns/prov#value | - FIG. 1 shows an overall structure of a multiprocessor system according to the present invention, and it comprises plural processor units 10-1 to 10-n (n is an integer larger than two), plural memories unit 700-1 to 700-m (m is an integer larger than two), units (not shown) which contain peripheral devices such as input-output devices and so on, and an interconnection network 50 which connects thos
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