About: http://webisa.webdatacommons.org/113623148

Property	Value
http://www.w3.org/1999/02/22-rdf-syntax-ns#type	http://www.w3.org/ns/prov#Entity
http://www.w3.org/ns/prov#value	The master latch circuit 22 shown in FIG. 16 is a dynamic latch circuit, and has the voltages of the internal output nodes OD1 and OD2 equalized when the transfer clock signal TG1 is at a high level.
http://www.w3.org/ns/prov#wasQuotedFrom	google.com