| http://www.w3.org/ns/prov#value | - how many of said plurality of in-series delay line elements has undergone a logic transition, and creating a contone variable having a numeric value equal to {number of delay line elements per system clock cycle}; and (d) using said contone variable to create at least one density signal having a logic state transition that occurs at times other than at a transition of said system clock. 28.
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