| http://www.w3.org/ns/prov#value | - The control circuit 5044 b shown in FIG. 118 activates the busy signal /BSYB (FIG. 121-(e)) according to the activation of the first-arrival signal /FSTA and the activation of the enable signal /ENA. In response to the busy signal /BSYB, a controller such as a CPU connected to the input/output port PORT-B ascertains that the active command ACT supplied to the multi-port memory M is invalid.
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