| http://www.w3.org/ns/prov#value | - wherein said memory cell is a dynamic memory cell including a storage capacitor and an address selection MOSFET, and wherein, by said metal option technique, an SDRAM is formed by a setting that addition capacitance is not connected to said input circuit or a DDR-SDRAM is formed by a setting that the addition capacitance is connected to said input circuit. 42.
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