| http://www.w3.org/ns/prov#value | - Similarly, FIG. 1B is a circuit diagram of a load resistance type voltage generating circuit constituted by a pMOS transistor PT and a resistance element RL. As shown in FIG. 1B, an inversion signal/Sin of an input signal Sin is applied to the gate of the pMOS transistor PT, and the source of the pMOS transistor is connected to a power-supply voltage Vcc.
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