| http://www.w3.org/ns/prov#value | - The variable byte multiplier circuit of claim 24 wherein:said byte adder circuitry includes a plurality of byte adders arranged in m said byte-additive stages, where m is the lowest integer satisfying the relationship 2m ???w, with each of the byte adders in a first one of the byte-additive stages receiving two of the second intermediate bytes and providing a single byte output to a byte
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