| http://www.w3.org/ns/prov#value | - In one embodiment, the node 10 (and more particularly the processors 12A-12N, the memory controller 14, the L2 cache 36, the interface circuits 20A-20C, the memory bridge 32 including the remote line directory 34, the packet DMA circuit 16, the switch 18, the configuration register 38, and the interconnect 22) may be integrated onto a single integrated circuit as a system on a chip configuration.
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