| http://www.w3.org/ns/prov#value | - In a second embodiment of the present invention, a memory device is provided comprising an array of rows and columns of memory cells and an address latch including a row address latch for latching a row address in response to a transition of a received row address strobe and a column address latch for latching a column address in response to a first transition of a received column address strobe.
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