| http://www.w3.org/ns/prov#value | - FIG. 5A is a diagram showing a latch circuit according to the second embodiment, the latch circuit including inverter circuits A and inverter circuits B. A latch circuit 100 shown in FIG. 5A includes an input terminal 101, transfer gates 102 and 103, inverter circuits A106, B107, A108, and B109, a transfer gate 104, and an output terminal 105.
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