| http://www.w3.org/ns/prov#value | - l oxide layer over said substrate including said trenches, a blanket thick floating gate layer of doped polysilicon over said tunnel oxide layer filling said trenches to below the top of said trenches, an interelectrode dielectric layer over said floating gate layer, and a control gate layer of doped polysilicon over said interelectrode dielectric layer. 18.
|
