| http://www.w3.org/ns/prov#value | - Writing to status register location 1430(W) also allows main processor 100 to both clear and interrupt and abort a transfer in progress (see FIG. 45A field 1434(1)). [0561]FIGS. 45F, 45G, 45H, 45I show additional registers main processor 100 can write to in order to control timing and other parameters of the peripheral interface bus 104.
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