| http://www.w3.org/ns/prov#value | - CNFET devices described further above with respect to FIGS. 59, 60, and 68 may be further enhanced with self aligned gates in combination with high dielectric insulators, doping of nanotube fabrics, gate insulators, gates, and contacts, using ion implantation, for example, and other methods described in incorporated U.S. patent application Ser.
|
