| http://www.w3.org/ns/prov#value | - This is true because when the phase shift between the CLKBUF and CLKFB signals is approximately zero (i.e., the delay-locked loop 100 is locked), the variable delay VD has a value of NTCK???(D1+D2) as indicated in FIG. 1, where N is an integer and TCK is the period of the CLK signal.
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