| http://www.w3.org/ns/prov#value | - As can easily be understood from the above description and FIGS. 2 to 5, in this embodiment, in the case that the latency N of the IC under test is an odd number, this case is processed such that an expected value signal and a comparison enable signal are delayed by the number of cycles expressed by (N???1)/2, and at the same time, a strobe signal is delayed by the sum (Tc+Tr) of the clock setting
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