| http://www.w3.org/ns/prov#value | - ted to the element B. A second adder 83D has one input directly connected to the input 800 of the interpolating circuit and another input connected to the output of the delay line 833 via a multiply-by-3 multiplier 85D. A divide-by-4 divider 84D is connected to the output of adder 83D and transmits an interpolation word PINT(P,L), relating to an element such as D, to an input of a reading AND gate
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