| http://www.w3.org/ns/prov#value | - to the pipeline clock line; N Narrow Pulse Triggered Latch (NPTL) stages with N sets of parallel single latches, with a set of parallel single latches in each stage, N Latch Pulse Generators (LPG)s and N???1 time delay units, where N is a positive integer; each of the NPTL stages comprising a single latch having with a latch data input, a latch data output and a latch clock input and a Latch Pulse
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