| http://www.w3.org/ns/prov#value | - tion of the memory bus, referred to as the upstream bus, returns requested read data and/or error, status or other operational information, and this information may be forwarded to the subsequent hub devices via bypass circuitry;be received, interpreted and re-driven if it is determined to be targeting an upstream hub device and/or memory controller in the processor complex; be re-driven in part o
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