| http://www.w3.org/ns/prov#value | - the semiconductor memory device of FIG. 1; [0036]FIG. 3 is a schematic block diagram of a semiconductor memory device according to a first embodiment of the present invention; [0037]FIG. 4 is a schematic block diagram of an internal operation determination circuit of the semiconductor of FIG. 3; [0038]FIG. 5 is a circuit diagram of a sense amplifier driver and a sense amplifier of the semiconduct
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