| http://www.w3.org/ns/prov#value | - The architecture includes N input ports 1-1 through 1-N, a plurality of cell memories 2-1 through 2-N together with an associated plurality of queue controls 3-1 through 3-N, contention control 7, and N???N switch 5 having both N switch input ports 4-1 through 4-N and N switch output ports 6-1 through 6-N. It should be noted that N is a positive integer greater than 1.
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