| http://www.w3.org/ns/prov#value | - the DRAM is in a standby mode. [0026] The delay locked loop circuit 15 illustrated in FIG. 1 is a circuit which may be used in a synchronous DRAM to generate an internal clock signal PCLK in synchronization with a system clock signal CLK. The DLL circuit 15 may consume significant amounts of power when it is activated (enabled).
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