| http://www.w3.org/ns/prov#value | - The controller 20 is structured as a microcomputer mainly including, as shown in FIG. 2, a Central Processing Unit (CPU) 21, a Read Only Memory (ROM) 22, a Random Access Memory (RAM) 23, and an Electrically Erasable and Programmable Memory (EEPROM) 24, and is connected to an Application Specific Integrated Circuit (ASIC) 26 via a bus 25.
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