| http://www.w3.org/ns/prov#value | - FIG. 5 is a timing chart illustrating the reset timing of a variable frequency divider and a fixed frequency divider during the band selection, in which FIG. 5A illustrates the reset timing of the same in the PLL circuit that was examined prior to this invention, and FIG. 5B illustrates the reset timing of the same in the PLL circuit in FIG. 1;
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