| http://www.w3.org/ns/prov#value | - A processing system including a processor and a coprocessor intercoupled by address and data buses, the coprocessor being operable to execute instructions in either I/O or memory mapped format presented by the processor, where, for an I/O format instruction, the processor provides the instruction opcode and the instruction operand over the data bus in successive bus cycles, and where, for a memory
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