| http://www.w3.org/ns/prov#value | - presence or absence of a standby state; a register for data; a counter having a multi-bit output; a control circuit responsive to the data in said register to repeatedly generate pulses of said digital masking signal having a duty cycle, said duty cycle responsive to the data in the register, said control circuit including a comparator having a first multibit input coupled to receive the data from
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