| http://www.w3.org/ns/prov#value | - The test chip will enable the correlation of the simulation models to the FinFET process and contains test structures, standard cells, a PLL and embedded SRAMs. The memory instances include high-density SRAMs designed to operate at very low voltages and high-speed SRAMs to validate the process performance.Antun Domic, senior VP and GM, Implementation Group, Synopsys said, Samsung is a key partner
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