| http://www.w3.org/ns/prov#value | - For synchronous, random logic in digital ICs and IC systems (boards), prior art built-in self test (BIST) schemes detect signal delays using at-speed scan test; for logic related to the pin interface circuitry located at the periphery of the IC, boundary scan is applied at or below the normal clock rate; and for memories such as SRAM, DRAM and ROM special patterns are applied at the normal opera
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